Higher performance, lower cost, increased miniaturization of electronic components, and greater density of integrated circuits are ongoing goals of the computer industry. One commonly used technique to increase density of integrated circuits involves stacking of multiple layers of active and passive components one atop another to allow for multi-level electrical interconnection between devices formed on each of these layers. This multi-level electrical interconnection is generally achieved with a plurality of metal-filled vias (“contacts”) extending through dielectric layers that separate the component layers from one another. These vias are generally formed by etching through each dielectric layer by etching methods known in the industry, such as plasma etching. Plasma etching is also used in the forming of a variety of features for the electronic components of integrated circuits.
As described in U.S. Pat. No. 6,544,895, incorporated herein by reference, in plasma etching, a glow discharge is used to produce reactive species, such as atoms, radicals, and/or ions, from relatively inert gas molecules in a bulk gas, such as a fluorinated gas, such as CF4, CHF3, C2F6, CH2F2, SF6, or other freons, and mixtures thereof, in combination with a carrier gas, such as Ar, He, Ne, Kr, O2, or mixtures thereof. Essentially, a plasma etching process comprises: 1) reactive species being generated in a plasma from the bulk gas, 2) the reactive species diffusing to a surface of a material being etched, 3) the reactive species absorbing on the surface of the material being etched, 4) a chemical reaction occurring that results in the formation of a volatile by-product, 5) the by-product being desorbed from the surface of the material being etched, and 6) the desorbed by-product diffusing into the bulk gas.
In a plasma etching chamber for semiconductor manufacturing, a plasma is maintained by coupling energy from a power source into the plasma, which comprises mobile positively and negatively charged particles. An electric field, or bias voltage, develops in a sheath layer around the plasma, accelerating the ions toward the semiconductor substrate by electrostatic coupling. Applying an oscillating bias power can modulate the potential difference between the plasma and the semiconductor substrate. The difference between an instantaneous plasma potential and a surface potential defines a sheath potential drop. During the positive voltage phase, the substrate collects an electron current from electrons that have enough energy to cross the sheath layer while during the negative voltage phase, positive ions are accelerated by the sheath voltage drop, strike the substrate, and are collected by the substrate.
However, plasma etching processes (as well as ion implantation and other charge beam processes) may damage the semiconductor substrate and the devices and circuits formed therein or thereon. In particular, electrical charging is a well-known problem that can occur during the plasma processing of semiconductor devices, leading to the degradation of the device performance.
FIG. 6 depicts the conventional phenomenon of electrical charging on a semiconductor device 240 in the process of a plasma etch. A material layer 244 to be etched is shown layered over a semiconductor substrate 242. A patterned photoresist layer 246 is provided on the material layer 244 for the etching of a via. During the plasma etching process, the patterned photoresist layer 246 and material layer 244 are bombarded with positively charged ions 248 and negatively charged electrons 252 (i.e., the reactive species). This bombardment results in a charge distribution being developed on the patterned photoresist layer 246 and/or the semiconductor substrate 242. This charge distribution is commonly called “feature charging.”
In order for feature charging to occur, the positively charged ions 248 and the negatively charged electrons 252 must become separated from one another. The positively charged ions 248 and negatively charged electrons 252 become separated by virtue of the structure being etched. As the structure (in this example a via 254) is formed by etching, the aspect ratio (height-to-width ratio) becomes greater and greater. During plasma etching, the positively charged ions 248 are accelerated (e.g., as a result of a DC bias at the semiconductor substrate 242) toward the patterned photoresist layer 246 and the material layer 244 in a relatively perpendicular manner, as illustrated by the arrows adjacent positively charged ions 248. The negatively charged electrons 252, however, are less affected by the DC bias at the semiconductor substrate 242 and, thus, move in a more random isotropic manner, as depicted by the arrows adjacent negatively charged electrons 252. This results in an accumulation of a positive charge at a bottom 256 of the via 254 because, on average, positively charged ions 248 are more likely to travel vertically toward the semiconductor substrate 242 than are negatively charged electrons 252. Thus, any structure with a high enough aspect ratio tends to charge more negatively at photoresist layer 246 and an upper portion of the material layer 244 to a distance A (i.e., illustrated with “−” indicia) and more positively at the via bottom 256 and the sidewalls 258 of the via 254 proximate the via bottom 256 (i.e., illustrated with “+” indicia).
As shown in drawing FIG. 7, the positively charged via bottom 256 deflects the positively charged ions 248 away from the via bottom 256 and toward the sidewalls 258 of the via 254, as a result of charge repulsion. The deflection results in an etching of the sidewalls 258 proximate the via bottom 256, which is known as “notching” or “twisting.” Furthermore, the presence of the positively charged via bottom 256 slows the positively charged ions 248 as they approach the positively charged via bottom 256, thereby reducing etching efficiency.
Current High Aspect Ratio Contacts (HARCs) are known to twist at aspect ratios greater than about 20:1. Twisting is the deviation of the bottom of a contact from the centerline of the etch front. Twisting is caused by asymmetric charge build-up in and around the contact, which causes a lateral deviation of the ion projectory. The twisting may be so serious that the etch processes actually generate corkscrew-shaped contacts. The twisting of the contact is a concern for shorting contacts to other structures or to each other. Certain tools and chemistries help reduce the twisting, but all known tools show this phenomenon.
Twisting is a current failure mechanism for contacts on 95 nm parts and has required extensive process developments to overcome. HARC etches are probably the most difficult etch needed on DRAM parts and have very tight constraints on profiles, film selectivities, and Critical Dimensions (CDs). The twisting behavior of contacts will limit the aspect ratio of contacts that can be etched in the near future and there is little research to understand this phenomena and no known solution to eliminate it.
In a standard plasma etch system the ion angular distribution is very anisotropic whereas the electron angular distribution is very isotropic. For HARC features, the electrons will mainly strike the contact near the top of the feature; while ions will reach the bottom of the feature. This is what causes the top of the contacts to charge negative, while the bottom of the contacts charge positive. Small asymmetries in the top of the contacts due to photolithography or polymer loading will cause asymmetric charging at the top of the contact leading to bending of the incident ions. This will then cause the contact to etch faster on one side of the contact due to increased ion flux to this area.